Aging Effects Analysis in Flip-Flops
نویسندگان
چکیده
This work presents a methodology to analyze aging effects in different flip-flops topologies. As CMOS transistor scaling to nanometer technologies in the last decades, new issues have become major concerns in VLSI design. One of those new issues is aging. Aging effects impact on performance and reliability of CMOS circuits. Flip-flops are one of the main structures in VLSI circuits. Their characteristics impact directly on circuit clock frequency, being also responsible for a large portion of the circuit power consumption. Experimental results show the impact of aging effects in three different FF topologies. An increment up to 15% in delay has been verified. Keywords— Flip-flops, aging effects, BTI, HCI, TDDB, digital circuits, CMOS.
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